1. Technical Field of the Invention
The present invention relates to an image display apparatus which is suitable for a flat display apparatus such as a liquid crystal display apparatus, and more particularly, relates to an image display apparatus which reduces the number of signal lines.
2. Description of the Related Art
As a liquid crystal display apparatus (LCD) is customarily demanded to use an increased number of pixels and accordingly realize high-speed driving, a plurality of data buses are used to meet this demand.
FIG. 1 is a schematic diagram showing an overall structure of a conventional liquid crystal display apparatus, FIG. 2 is a block diagram showing a relationship between source drivers and a timing controller and the like in the conventional liquid crystal display apparatus, FIG. 3 is a schematic diagram showing a relationship between data buses and data lines, FIG. 4 is a block diagram of a conventional source driver, FIG. 5 is a circuitry diagram of a conventional shift register, and FIG. 6 is a block diagram showing a relationship between a conventional data register and a timing controller.
As shown in FIG. 1, in the liquid crystal display apparatus, n pieces of tape carrier packages (TCP) 102 are connected to source lines (not shown) which run in the vertical direction in a liquid crystal panel 101 and m pieces of TCPs 103 are connected to gate lines (not shown) which run in the horizontal direction in the liquid crystal panel 101. The liquid crystal panel 101 is obtained by sealing up liquid crystals between glass substrates for instance and incorporating a thin film transistor (TFT) and the like. The TCPs 102 each seat one of source drivers 104-1 through 104-n, while the TCPs 103 each seat one of gate drivers 105-1 through 105-m. Each TCP 102 is connected to a signal processing substrate 107 which mounts a timing controller 106, and each TCP 103 is connected to a vertical-side connection substrate 108. The signal processing substrate 107 and the vertical-side connection substrate 108 are formed by printed circuit boards, for example. An interface connector 109 and a flexible printed circuit board (FPC) 110 are disposed to the signal processing substrate 107. Connected to the interface connector 109 are a display cable (not shown) to which pixel data and the like are transferred, etc. The signal processing substrate 107 and the vertical side connection substrate 108 are bent toward the back side of the liquid crystal panel 101 utilizing the flexibility of the TCPs 102 and 103 respectively, which connects the FPC 110 to the vertical-side connection substrate 108.
As shown in FIG. 2, a video signal outputted from the interface connector 109 is supplied to the respective source drivers 104-1 through 104-n from the timing controller 106 through a data bus group 111. The data bus group 111 is comprised of two data buses for instance. Further, each data bus is formed by six data lines each for red, green and blue, i.e., eighteen data lines as shown in FIG. 3 in the event that pixel data are a 6-bit signal. Hence, where the data bus group 111 is comprised of two data buses for instance, there are thirty-six data lines between the timing controller 106 and each source driver. In the event that pixel data are an 8-bit signal, the data buses are each formed by twenty-four data lines. A clock signal line 112, an inversion signal line 113 and a data latch signal line 114 are connected between the timing controller 106 and each source driver, a clock signal CLK is supplied to each source driver on the clock signal line 112, an inversion signal POL2 is supplied to each source driver on the inversion signal line 113, and a data latch signal STB is supplied to each source driver on the data latch signal line 114. Further, a shift signal line 115 is connected between the timing controller 106 and only the source driver 104-1, and a cascade signal line 116 is connected between the adjacent source drivers. A shift signal STH is supplied to the source driver 104-1 on the shift signal line 115, whereby this shift signal STH is shifted as a cascade signal across the source drivers one after another.
In addition, a gradation level power source 117 which supplies a gradation level voltage to each source driver is disposed in the liquid crystal display apparatus.
In the event that pixel data are a 6-bit signal, a 64-bit bi-directional shift register 121, a data register 122, a latch circuit 123, a level shifter 124, a digital/analog (D/A) converter 125 and an output buffer 126 are disposed in a conventional source driver as shown in FIG. 4.
A signal R/L which determines the direction in which the shift signal STH is shifted is supplied to the shift register 121. The logic of this signal R/L decides which one of a terminal STHR and a terminal STHL will serve as an input terminal or an output terminal for the shift signal. The shift register 121 also receives the clock signal CLK which determines the timing at which pixel data are loaded and the data latch signal STB which resets an internal flip-flop of the shift register 121 after being outputted from the timing controller 106 at the timing for loading data which are equivalent to one line.
As shown in FIG. 5, sixty-four D-type flip flops DFF101 through DFF164 which are directly connected with each other are disposed in the shift register 121. The clock signal CLK is supplied to a CK-terminal for each one of the D-type flip flops DFF101 through DFF164. In the case that the terminal STHR is to serve as the input terminal for the shift signal STH, an output signal from a logical multiplication gate AND101 is fed to a D-terminal of the first-stage D-type flip flop DFF101. Meanwhile, a QB-terminal of each one of the D-type flip flops DFF101 through DFF164 and the terminal STHR are connected to an input terminal of the logical multiplication gate AND101. As described herein, the “QB-terminal” refers to a terminal which is usually denoted as the letter “Q” directly under the bar (−) sign, and is denoted at the letter “Q” right under the bar (−) sign in the drawings as is normally denoted.
In the shift register 121 having such a structure, output signals from the respective Q-terminals of the D-type flip flops DFF101 through DFF164 become output signals C1 through C64.
The data register 122 receives pixel data of (six bits)×(three colors)×(two data buses), i.e., sixty-four bits in total which are D00 through D05, D10 through D15, D20 through D25, D30 through D35, D40 through D45 and D50 through D55. Further, the data register 122 receives inversion signals POL21 and POL22 which are assigned as the inversion signal POL2 respectively to the two data buses.
As shown in FIG. 6, there are an inversion/non-inversion circuit 131 which receives the pixel data outputted from the timing controller 106 via the data bus group 111 and a register 132 which stores output data from the inversion/non-inversion circuit 131. The inversion signal POL2 as well is supplied to the inversion/non-inversion circuit 131, and when the inversion signal POL2 is active, the pixel data supplied to the inversion/non-inversion circuit 131 are inverted and outputted to a register 132. On the other hand, when the inversion signal POL2 is not active, the pixel data supplied to the inversion/non-inversion circuit 131 are outputted as they are to the register 132. The timing controller 106 comprises a bit comparator 133 which compares data to be transmitted from now and data which were transmitted immediately previously, and an inversion/non-inversion circuit 134 which inverts pixel data in accordance with an output signal from the bit comparator 133 and outputs the pixel data.
In the conventional liquid crystal display apparatus having such a structure, the bit comparator 133 disposed within the timing controller 106 detects how many bits of change has been created between the pixel data to be transmitted from now and the pixel data which were transmitted right before this pixel data, and in the event that half or more of the pixel data has changed, the inversion/non-inversion circuit 134 is provided with a signal which requires the inversion/non-inversion circuit 134 to invert and output the pixel data. Receiving this signal, the inversion/non-inversion circuit 134 inverts the pixel data and outputs the pixel data via the data bus group 111 while outputting the active inversion signal POL2 to the inversion/non-inversion circuit 131 on the inversion signal line 113.
FIG. 7 is a timing chart showing an operation of the conventional shift register 121. As the shift signal STH is received at the terminal STHR, the shift register 121 outputs at the terminals C1 through C64 timing pulses which are for loading the pixel data into the data register 122 in synchronization to rises of the clock signal CLK starting at the next rise of the clock signal CLK. Concurrently with outputting of the timing pulse at the terminal C64, the shift signal STH is outputted at the terminal STHL to the next-stage source driver. In the liquid crystal display apparatus shown in FIG. 5, the shift signal STH from the timing controller 106 is supplied as a start pulse to the shift register 121 of only the source driver 104-1, and the shift registers 121 of the other source drivers are provided with the shift signal STH which is shifted on the cascade signal line 116 from the preceding-stage source driver.
In synchronization to the timing pulse from the shift register 121, the data register 122 stores the pixel data D00 through D05, D10 through D15, D20 through D25, D30 through D35, D40 through D45 and D50 through D55 in the register 132. However, when the inversion signal POL21 or POL22 is active, the inversion/non-inversion circuit 131 inverts the pixel data which were received on one of the two data buses forming the data bus group 111 which corresponds to the active inversion signal, and stores the pixel data in the register 132. Since this method reduces the amount of changes in the digital signals which are transmitted on the data buses, electromagnetic interference (EMI) is reduced and electric power used for charging and discharging of the data buses is decreased. The data register 122 stores signals amounting to 384 bits, i.e., (sixty-four bits)×(two data buses)×(three colors).
In order to output the gradation level voltages to all source drivers 104-1 through 104-n at the same time, the latch circuit 123 holds data which are equivalent to one line until outputting of the same. A polarity inversion signal POL for inverting the polarity of a signal for every frame for the purpose of a.c. driving of the liquid crystal panel is supplied to the latch circuit 123 and the output buffer 126.
Following this, the level shifter 124 converts the logic level of the pixel data, and the D/A converter 125 receiving the gradation level voltages V0 through V9 converts the digital signals into analog signals. Tone level voltages (analog) are then applied to the source lines for the liquid crystal panel 101 from terminals S1 through S384 which are disposed to the output buffer 126.
In the liquid crystal panel 101, the gate lines are scanned over line by line owing to the gate drivers 105-1 through 105-m, and in synchronization to the timing of the scanning, the gradation level voltages are applied to the source lines simultaneously from the respective source drivers 104-1 through 104-n, whereby displaying is realized at the respective pixels on the voltage-applied source lines.
The liquid crystal display apparatus may be a liquid crystal display apparatus in which there is only one data bus disposed and pixel data are stored in a data register in synchronization to a rise in a clock signal (FIG. 8A), a liquid crystal display apparatus in which there are two data buses disposed and pixel data are stored from both data buses into a data register in synchronization to rising of a clock signal (FIG. 8B), a liquid crystal display apparatus in which there are two data buses disposed and pixel data are stored from each data bus into a data register in synchronization to rising/falling of a clock signal (FIG. 8C), etc.
Japanese Unexamined Patent Publication No. 8-8991 of 1996 describes, in relation to transfer of data in an image display apparatus or the like, a data transfer apparatus which reduces the frequency of switching or the like to thereby reduce consumption current. Disclosed in this publication are a data transfer apparatus in which a clock signal is masked in the absence of a change in data for instance and a data transfer apparatus in which data are transmitted after being inverted in the event of a change in a majority of bits. In a data transfer apparatus in which data are inverted and transmitted in the event of a change in a majority of bits, a 1-bit signal similar to the inversion signal POL2 used in the conventional liquid crystal display apparatus shown in FIG. 8 is generated within a controller and transmitted together with data to a receiving apparatus. This 1-bit signal as well is transmitted on a dedicated signal line. Use of these data transfer apparatuses makes it possible to reduce consumption current.
However, the conventional liquid crystal display apparatus is demanded, because of an improvement in resolution, a higher frequency of the clock signal and an enhancement in transfer speed of pixel data, and therefore, uses more than one data bus as described above. For this reason, it is necessary to use an accordingly increased number of inversion signal lines, and hence, dispose a greater number of pins in LSIs (large-size integrated circuits) which form the timing controller and the source drivers. This leads to a problem in that the size of an LSI package becomes large. In addition, the gaps between the signal lines become narrower as more signal lines are used, which in turn intensifies the influence by mutual inductance and capacitance. Hence, the possibility of malfunction due to cross talk (deterioration in waveform quality) rises. Further, the number of steps for design of a substrate pattern increases in accordance with the increase in the number of signal lines.
These problems are inherent to the data transfer apparatuses which are described in Japanese Unexamined Patent Publication No. 8-8991 of 1996 which aim at a reduction in consumption current or the like. As the number of data buses increases in accordance with an increase in transfer speed, it is necessary to accordingly increase the number of signal lines.